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TDA8034T; TDA8034AT
Smart card interface
Rev. 2.0 -- 12 November 2010 Product data sheet
1. General description
The TDA8034T/TDA8034AT is a cost-effective analog interface for asynchronous and synchronous smart cards operating at 5 V or 3 V. Using few external components, the TDA8034T/TDA8034AT provides all supply, protection and control functions between a smart card and the microcontroller.
2. Features and benefits
Integrated circuit smart card interface in an SO16 package 5 V or 3 V smart card supply One protected half-duplex bidirectional buffered I/O line (C7) VCC regulation: 5 V 5 % or 3 V 5 % using two low ESR multilayer ceramic capacitors: one of 220 nF and one of 470 nF current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to 20 MHz, with controlled rise and fall times and filtered overload detection of approximately 120 mA Thermal and short-circuit protection for all card contacts Automatic activation and deactivation sequences triggered by a short-circuit, card take-off, overheating, falling VDD, VDD(INTF) or VDDP Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV External clock input up to 26 MHz connected to pin XTAL1 Card clock generation up to 20 MHz using pin CLKDIV1 with synchronous frequency changes of: 1 f 1 2 xtal or 4 fxtal on TDA8034T fxtal or 12 fxtal on TDA8034AT Non-inverted control of pin RST using pin RSTIN Compatible with ISO 7816, NDS and EMV 4.2 payment systems Supply supervisor for killing spikes during power on and off: using a fixed threshold using an external resistor bridge with threshold adjustment Built-in debouncing on card presence contacts (typically 4.5 ms) Multiplexed status signal using pin OFFN
3. Applications
Pay TV Electronic payment
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
Identification Bank card readers
4. Quick reference data
Table 1. Quick reference data VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Supply VDDP VDD VDD(INTF) IDD IDDP power supply voltage supply voltage interface supply voltage supply current power supply current pin VDDP pin VDD pin VDD(INTF) Shutdown mode Shutdown mode; fxtal stopped Active mode; fCLK = 12 fxtal; no load IDD(INTF) VCC interface supply current
[1]
Parameter
Conditions
Min 4.85 2.7 1.6 -
Typ 5 3.3 3.3 -
Max 5.5 3.6 VDD + 0.3 35 5 1.5 6
Unit V V V A A mA A
Shutdown mode active mode 5 V card ICC < 65 mA DC current pulses of 40 nA/s at ICC < 200 mA; t < 400 ns
Card supply voltage: pin VCC
supply voltage
4.75 4.65
5.0 5.0
5.25 5.25
V V
Vripple(p-p) ICC General tdeact Ptot Tamb
[1]
peak-to-peak ripple voltage supply current deactivation time total power dissipation ambient temperature
from 20 kHz to 200 MHz VCC = 0 V to 5 V or 3 V see Figure 7 on page 10 Tamb = -25 C to +85 C
35 -25
90 -
350 65 250 0.25 +85
mV mA s W C
To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 220 nF and one 470 nF.
5. Ordering information
Table 2. Ordering information Package Name TDA8034T TDA8034AT SO16 Description plastic small outline package; 16 leads; body width 3.9 mm Version SOT109-1 Type number
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
2 of 29
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
6. Block diagram
10 F 100 nF 100 nF
VDD 14 SUPPLY
GND 9
VDDP 13
INTERNAL REFERENCE VOLTAGE SENSE PRESN RSTIN CMDVCCN OFFN CLKDIV1 7 4
INTERNAL OSCILLATOR CLKUP ALARMN EN1 PVCC VCC LDO 12 VCC
470 nF 220 nF
SEQUENCER 5 15 6 CLOCK CIRCUITRY CLK LEVEL SHIFTER EN4 RESET GENERATOR CLOCK GENERATOR CMDVCCN DETECTION THERMAL PROTECTION I/O TRANSCEIVER
11 RST
EN3 EN2 10 CLK CARD CONNECTOR C5 C6 8 I/O C7 C8 CRYSTAL OSCILLATOR C1 C2 C3 C4
I/OUC
16
TDA8034T TDA8034AT
3 VDD(INTF)
100 nF
1 XTAL1
2 XTAL2
001aak989
Fig 1.
Block diagram
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
3 of 29
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
7. Pinning information
7.1 Pinning
XTAL1 XTAL2 VDD(INTF) RSTIN CMDVCCN CLKDIV1 PRESN I/O
1 2 3 4 5 6 7 8
001aak990
16 I/OUC 15 OFFN 14 VDD
TDA8034T TDA8034AT
13 VDDP 12 VCC 11 RST 10 CLK 9 GND
Fig 2.
Pin configuration (SO16)
7.2 Pin description
Table 3. Symbol XTAL1 XTAL2 VDD(INTF) RSTIN CLKDIV1 PRESN I/O GND CLK RST VCC VDDP VDD OFFN I/OUC
[1] [2] [3] [4]
Pin description Pin Supply 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 VDD VDD Type[1] Description I O crystal connection input crystal connection output interface supply voltage microcontroller card reset input; active HIGH microcontroller start activation sequence input; active LOW sets the clock frequency on pin CLK; see Table 4 on page 7 card presence contact input; active LOW[2] card input/output data line (C7)[3] ground card clock (C3) card reset (C2) card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin VCC and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m[4] low-dropout regulator input supply voltage digital supply voltage NMOS interrupt to microcontroller[5]; active LOW; see Section 8.9 on page 10 microcontroller input/output data line[6]
VDD(INTF) P VDD(INTF) I VDD(INTF) I VDD(INTF) I VDD(INTF) I VCC VCC VCC VCC VDDP VDD I/O G O O P P P
CMDVCCN 5
VDD(INTF) O VDD(INTF) I/O
I = input, O = output, I/O = input/output, G = ground and P = power supply. If pin PRESN is HIGH, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8034T/TDA8034AT has a built-in debouncing timer (typically 4.5 ms). Uses an internal 11 k pull-up resistor connected to pin VCC. Using a 220 nF capacitor increases the noise margin on pin VCC.
All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
TDA8034T_TDA8034AT
Product data sheet
Rev. 2.0. -- 12 November 2010
4 of 29
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
[5] [6]
Uses an internal 20 k pull-up resistor connected to pin VDD(INTF). Uses an internal 10 k pull-up resistor connected to pin VDD(INTF).
8. Functional description
Remark: Throughout this document the ISO 7816 terminology conventions have been adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The power supply voltage ranges are as follows:
* VDDP: 4.85 V to 5.5 V * VDD: 2.7 V to 3.6 V
All interface signals to the system controller are referenced to VDD(INTF). All card contacts remain inactive during power up or power down. After powering up the device, pin OFFN remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth). The internal oscillator frequency (fosc(int)) is only used during the activation sequences. When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low frequency mode to reduce power consumption. This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the power supply voltage on pin VDDP does not fall below 4.85 V for a maximum load current of 65 mA.
8.2 Voltage supervisor
VDD(INTF) VDD VDD REFERENCE VOLTAGE
VDDP
5 V or 3 V
001aak991
Fig 3.
TDA8034T_TDA8034AT
Voltage supervisor circuit
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Product data sheet
Rev. 2.0. -- 12 November 2010
5 of 29
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
The voltage supervisor monitors the voltage of the VDDP and VDD supplies providing both Power-On Reset (POR) and supply drop-out detection during a card session. The supervisor threshold voltages for VDDP and VDD are set internally. As long as VDD is less than Vth + Vhys, the IC remains inactive irrespective of the command line levels. After VDD has reached a level higher than Vth + Vhys, the IC remains inactive for the duration of tw. The output of the supervisor is sent to a digital controller in order to reset the TDA8034T/TDA8034AT. This defined reset pulse of approximately 8 ms, i.e. (tw = 1024 x 1 fosc(int)low), is used internally to maintain the IC in the Shutdown mode during the supply voltage power on; see Figure 4. A deactivation sequence is performed when either VDD or VDDP falls below Vth. Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int) parameter.
Vth + Vhys Vth VDD
ALARMN (internal signal) power on
tw
tw supply dropout
power off
001aak993
Fig 4.
Voltage supervisor waveforms
8.3 Clock circuits
The clock signal from pin CLK to the card is either supplied by an external clock signal connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and XTAL2. The TDA8034T/TDA8034AT automatically detects if an external clock is connected to XTAL1, eliminating the need for a separate pin to select the clock source. Automatic clock source detection is performed on each activation command (falling edge of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is checked during a time window defined by the internal oscillator. If a clock is detected, the internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator is started. When an external clock is used, it is mandatory that the clock is applied to pin XTAL1 before the falling edge of the signal on pin CMDVCCN.
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
DIGITAL enclkin clkxtal MULTIPLEXER
CRYSTAL
XTAL1
XTAL2
001aak992
enclkin and clkxtal are internal signal names.
Fig 5.
Basic layout for using an external clock
The clock frequency is selected using pin CLKDIV1 to be either 12 fxtal or 14 fxtal on TDA8034T or fxtal or 12 fxtal on TDA8034AT as shown in Table 4. The frequency change is synchronous and as such during transition, no pulse is shorter than 45 % of the smallest period. In addition, only the first and last clock pulse around the change has the correct width. When dynamically changing the frequency, the modification is only effective after 10 clock periods on pin XTAL1. The duty cycle of fxtal on pin CLK should be between 45 % and 55 %. If an external clock is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %. When the frequency of the clock signal on pin CLK is either 12 fxtal or 14 fxtal on TDA8034T or fxtal or 12 fxtal on TDA8034AT, the frequency dividers guarantee a duty cycle between 45 % and 55 %.
Table 4. Clock configuration Pin CLK level TDA8034T HIGH LOW
1 f 2 xtal 1 f 4 xtal
Pin CLKDIV1 level
TDA8034AT
1 f 2 xtal
fxtal
8.4 Input and output circuits
When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC VDD(INTF). The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables falling edge detection on the other line, making it the slave. After a time delay td, the logic 0 present on the master-side is sent to the slave-side. When the master-side returns logic 1, the slave-side sends logic 1 during time delay (tw(pu)). After this sequence, both master and slave sides return to their idle states. The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of 0.9VCC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the internal pull-up resistor value and load current. The current sent to and received from the card's I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
7 of 29
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
8.5 Shutdown mode
After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode, ensuring only the minimum number of circuits are active while the TDA8034T/TDA8034AT waits for the microcontroller to start a session.
* all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
* * * *
pin I/OUC is high-impedance using the 11 k pull-up resistor connected to VDD(INTF) the voltage generators are stopped the voltage supervisor is active the internal oscillator runs at its lowest frequency (fosc(int)low)
8.6 Activation sequence
The following device activation sequence is applied when using an external clock; see Figure 6: 1. Pin CMDVCCN is pulled LOW (t0). 2. The internal oscillator is triggered (t0). 3. The internal oscillator changes to high frequency (t1). 4. VCC rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2). 5. Pin I/O is driven HIGH (t3). 6. The clock on pin CLK is applied to the C3 contact (t4). 7. Pin RST is enabled (t5). Calculation of the time delays is as follows:
* * * * *
t1 = t0 + 384 x 1fosc(int)low t2 = t1 t3 = t1 + 17T / 2 t4 = driven by host controller; > t3 and < t5 t5 = t1 + 23T / 2
Remark: The value of period T is 64 times the period interval of the internal oscillator at high frequency (1fosc(int)high); t3 is called td(start) and t5 is called td(end).
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
CMDVCCN XTAL VCC I/O ATR
CLK > 200 ns RSTIN
RST
I/OUC
OSCINT
low frequency t0 t1 = t2 t4 td(start) td(end) = tact
high frequency
001aai966
OSCINT = internal oscillator.
Fig 6.
Activation sequence at t3
8.7 Deactivation sequence
When a session ends, the microcontroller sets pin CMDVCCN HIGH. The TDA8034T/TDA8034AT then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see Figure 7) as follows: 1. Pin RST is pulled LOW (t11). 2. The clock is stopped, pin CLK is LOW (t12). 3. Pin I/O is pulled LOW (t13). 4. VCC falls to 0 V (t14). The deactivation sequence is completed when VCC reaches its inactive state. 5. VCC < 0.4 V (tdeac) 6. All card contacts become low-impedance to GND. However, pin I/OUC remains pulled up to VDD using the 11 k resistor. 7. The internal oscillator returns to its low frequency mode. Calculation of the time delays is as follows:
* * * * *
t11 = t10 + 3T / 64 t12 = t11 + T / 2 t13 = t11 + T t14 = t11 + 3T / 2 tdeac = t11 + 3T / 2 + VCC fall time
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e. 25 s).
CMDVCC
RST
CLK
I/O
VCC XTAL1
OSCINT
high frequency t10 t11 t12 tdeact t13 t14
low frequency
001aak995
OSCINT = internal oscillator.
Fig 7.
Deactivation sequence
8.8 VCC regulator
The VCC buffer is able to continuously deliver up to 65 mA at VCC = 5 V or 3 V. The VCC buffer has an internal overload protection with a threshold value of approximately 120 mA. This detection is internally filtered, enabling spurious current pulses up to 200 mA with a duration of a few milliseconds to be drawn by the card without causing deactivation. However, the average current value must stay below maximum; see Table 8.
8.9 Fault detection
The following conditions are monitored by the fault detection circuit:
* * * * * *
Short-circuit or high current on pin VCC Card removal during transaction VDDP falling VDD falling VDD(INTF) falling Overheating
Fault detection monitors two different situations:
* Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any voltage drop on VDD is detected by the voltage supervisor. This generates an internal power-on reset pulse but does not act upon the pin OFFN signal. The card is not powered-up and short-circuits or overheating are not detected.
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
* In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault
detection circuit triggers the automatic emergency deactivation sequence (see Figure 8). When the microcontroller resets pin CMDVCCN to HIGH, after the deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN returns to HIGH. This check identifies the fault as either a hardware problem or a card removal incident. On card insertion or removal, bouncing can occur in the PRESN signal. This depends on the type of card presence switch in the connector (normally open or normally closed) and the mechanical characteristics of the switch. To correct for this, a debouncing feature is integrated in to the TDA8034T/TDA8034AT. This feature operates at a typical duration of 4.5 ms (tdeb = 640 x (1fosc(int)low). Figure 9 on page 12 shows the operation of the debouncing feature. On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the card is extracted, the automatic card deactivation sequence is performed on the first HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW.
OFFN PRESN
RST CLK I/O VCC XTAL
OSCINT t10
high frequency t12 t13 tdeact t14
low frequency
001aai971
Fig 8.
Emergency deactivation sequence after card removal
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
PRESN
OFFN
CMDVCCN tdeb VCC
(1)
tdeb
(2) 001aal411
(1) Deactivation caused by card withdrawal. (2) Deactivation caused by short-circuit.
Fig 9.
Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and VCC
8.10 Automatic determining of card supply voltage
The supply voltage (VCC) that the card requires is determined automatically by monitoring the duration of the HIGH state (logic 1) on pin CMDVCCN before the activation command (CMDVCCN falling edge) occurs. If pin CMDVCCN stays HIGH for more than 30 ms, activation occurs with VCC set to 5 V. If pin CMDVCCN stays HIGH for less than 15 ms, activation occurs with VCC set to 3 V. To activate the card at VCC = 5 V, pin CMDVCCN must stay HIGH for t0 > 30 ms before going LOW (logic 0).
CMDVCCN t0 3 V or 5 V VCC 5V
001aak998
Fig 10. Card activation, VCC = 5 V, t0 > 30 ms
To activate the card at VCC = 3 V, pin CMDVCCN must stay HIGH for t0 < 15 ms before going LOW (logic 0).
CMDVCCN t0 3 V or 5 V VCC 3V
001aak999
Fig 11. Card activation, VCC = 3 V, t0 < 15 ms
If pin CMDVCCN is HIGH for more than 15 ms (t0 > 15 ms) but less than 30 ms, pin CMDVCCN must be set LOW for t1 (200 s < t1 < 700 s), and then HIGH for t2 (200 s < t2 < 15 ms) before going LOW.
TDA8034T_TDA8034AT
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Product data sheet
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
CMDVCCN t0 3 V or 5 V VCC t1 t2 3V
001aal000
Fig 12. Card activation, VCC = 3 V, t0 > 15 ms
If pin CMDVCCN is HIGH for more than 30 ms (card inactive), and if the card needs to be activated at 3 V, the sequence shown in Figure 12 applies: pin CMDVCCN must be set LOW for t1 (200 s < t1 < 700 s), and then HIGH for t2 (200 s < t2 < 15 ms) before going LOW.
9. Limiting values
Remark: All card contacts are protected against any short-circuit to any other card contact. Stress beyond the levels indicated in Table 5 can cause permanent damage to the device. This is a short-term stress rating only and under no circumstances implies functional operation under long-term stress conditions.
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDP VDD VDD(INTF) VI Parameter power supply voltage supply voltage interface supply voltage input voltage Conditions pin VDDP pin VDD pin VDD(INTF) pins CMDVCCN, CLKDIV1, RSTIN, OFFN, XTAL1, XTAL2, I/OUC card contact pins PRESN, I/O, RST and CLK Tstg Ptot Tj Tamb VESD storage temperature total power dissipation junction temperature ambient temperature electrostatic discharge voltage Human Body Model (HBM) on card pins I/O, RST, VCC, CLK, PRESN; within typical application Human Body Model (HBM); all other pins Machine Model (MM); all pins Field Charged Device Model (FCDM); all pins Tamb = -25 C to +85 C Min -0.3 -0.3 -0.3 -0.3 -0.3 -55 -25 -6 Max +6 +4.6 +4.6 +4.6 +6 +150 0.25 +125 +85 +6 Unit V V V V V C W C C kV
-2 -200 -500
+2 +200 +500
kV V V
10. Thermal characteristics
Table 6. Symbol Rth(j-a) Thermal characteristics Package name SO16 Parameter thermal resistance from junction to ambient Conditions in free air Typ 94 Unit K/W
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
11. Characteristics
Table 7. Characteristics of IC supply voltage VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Supply VDDP VDD VDD(INTF) IDD IDDP power supply voltage supply voltage supply current power supply current pin VDDP pin VDD Shutdown mode Shutdown mode fxtal stopped Active mode fCLK = 12 fxtal; no load fCLK = 2 fxtal; ICC = 65 mA IDD(INTF) Vth Vhys tw Cdec Vo interface supply current Shutdown mode threshold voltage hysteresis voltage pulse width
[1] [2] 1
Parameter
Conditions
Min 4.85 2.7 1.6 2.30 3.00 50 100 5.1 550 -0.1 -0.1 -
Typ 5 3.3 3.3 2.40 4.10 100 200 8 -
Max 5.5 3.6 VDD + 0.3 35 5 1.5 70 6 2.50 4.40 150 350 10.2 830 +0.1 +0.3 -1
Unit V V V A A mA mA A V V mV mV ms nF V V mA
interface supply voltage pin VDD(INTF)
pin VDD pin VDDP pin VDD pin VDDP
Card supply voltage: pin VCC output voltage
decoupling capacitance connected to VCC Shutdown mode no load Io = 1 mA
Io VCC
output current supply voltage
Shutdown mode; pin VCC connected to ground active mode 5 V card ICC < 65 mA DC current pulses of 40 nA/s at ICC < 200 mA; t < 400 ns 3 V card ICC < 65 mA DC current pulses of 40 nA/s at ICC < 200 mA; t < 400 ns
4.75 4.65
5.0 5.0
5.25 5.25
V V
2.85 2.76
3.05 -
3.15 3.20
V V
Vripple(p-p) peak-to-peak ripple voltage ICC supply current
20 kHz to 200 MHz VCC = 0 V to 5 V or 3 V VCC shorted to ground
90
120
350 65 150
mV mA mA
TDA8034T_TDA8034AT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2.0. -- 12 November 2010
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NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
Table 7. Characteristics of IC supply voltage ...continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol SR Parameter slew rate Conditions 5 V card 3 V card Crystal oscillator: pins XTAL1 and XTAL2 Cext external capacitance pins XTAL1 and XTAL2 (depending on the crystal or resonator specification) card clock reference; crystal oscillator external clock on pin XTAL1 crystal oscillator external clock crystal oscillator external clock falling edge on pins I/O and I/OUC or vise versa on data lines on data lines Shutdown mode no load Io = 1 mA Io VOL VOH output current LOW-level output voltage HIGH-level output voltage Shutdown mode; pin I/O grounded IOL = 1 mA IOL 15 mA no DC load IOH < -40 A IOH -15 mA VIL VIH Vhys IIL IIH tr(i) tr(o) LOW-level input voltage HIGH-level input voltage hysteresis voltage HIGH-level input current input rise time output rise time VCC = +5 V VCC = +3 V pin I/O pin I/O; VIH = VCC VIL maximum to VIH minimum CL 80 pF; 10 % to 90 %; 0 V to VCC 0 0 0 VCC - 0.4 0.9VCC 0.75VCC 0 -0.3 0.6VCC 0.7VCC 50 0.1 0.3 -1 0.3 VCC VCC + 0.1 VCC + 0.1 0.4 +0.8 VCC + 0.3 VCC + 0.3 600 10 1.2 0.1 V V mA V V V V V V V V mV A A s s 15 pF Min 0.055 0.040 Typ 0.180 0.180 Max 0.300 0.300 Unit V/s V/s
fxtal fext VIL VIH
crystal frequency external frequency LOW-level input voltage HIGH-level input voltage
2 0 -0.3 -0.3 0.7VDD 0.7VDD(INTF) 200 -
-
26 26 +0.3VDD +0.3VDD(INTF) VDD + 0.3 VDD(INTF) + 0.3 200 400 1 10
MHz MHz V V V V ns ns MHz pF
Data lines: pins I/O and I/OUC td tw(pu) fio Ci Vo delay time pull-up pulse width input/output frequency input capacitance output voltage
Data lines to the card: pin I/O[3]
LOW-level input current pin I/O; VIL = 0 V
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Table 7. Characteristics of IC supply voltage ...continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol tf(i) tf(o) Rpu Ipu VOL VOH Parameter input fall time output fall time pull-up resistance pull-up current LOW-level output voltage HIGH-level output voltage Conditions VIL maximum to VIH minimum CL 80 pF; 10 % to 90 %; 0 V to VCC connected to VCC VOH = 0.9VCC; C = 80 pF I/OUC[4] IOL = 1 mA no DC load IOH 40 A; VDD(INTF) > 2 V IOH 20 A; VDD(INTF) < 2 V VIL VIH Vhys IIH IIL Rpu tr(i) tr(o) tf(i) tf(o) Ipu fosc(int) LOW-level input voltage HIGH-level input voltage hysteresis voltage HIGH-level input current pull-up resistance input rise time output rise time input fall time output fall time pull-up current internal oscillator frequency pin I/OUC VIH = VDD(INTF) 0 0.9VDD(INTF) 0.3 VDD(INTF) + 0.1 VDD(INTF) + 0.1 VDD(INTF) + 0.1 +0.3VDD(INTF) VDD(INTF) + 0.3 10 600 12 1.2 0.1 1.2 0.1 200 3.2 V V V V V V V A A k s s s s mA kHz MHz Min 7 -8 Typ 9 -6 Max 1.2 0.1 11 -4 Unit s s k mA
Data lines to the system: pin
0.75VDD(INTF) 0.75VDD(INTF) -0.3 0.7VDD(INTF) 8 -1 100 2 0.14VDD(INTF) 10 150 2.7
LOW-level input current VIL = 0 V connected to VDD(INTF) VIL maximum to VIH minimum CL 30 pF; 10 % to 90 %; 0 V to VDD(INTF) VIL maximum to VIH minimum CL 30 pF; 10 % to 90 %; 0 V to VDD(INTF) VOH = 0.9VDD; C = 30 pF Shutdown mode active state Shutdown mode no load Io = 1 mA
Internal oscillator
Reset output to the card: pin RST Vo output voltage 0 0 0.1 0.3 -1 2 V V mA s
Io td
output current delay time
Shutdown mode; pin RST grounded between pins RSTIN and RST; RST enabled
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Table 7. Characteristics of IC supply voltage ...continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol VOL Parameter LOW-level output voltage Conditions IOL = 200 A; VCC = +5 V IOL = 200 A; VCC = +3 V current limit IOL = 20 mA VOH tr tf Vo HIGH-level output voltage rise time fall time output voltage IOH = -200 A current limit IOH = -20 mA CL = 100 pF CL = 100 pF Shutdown mode no load Io = 1 mA Io VOL VOH tr tf fCLK SR output current LOW-level output voltage HIGH-level output voltage rise time fall time frequency on pin CLK duty cycle slew rate Shutdown mode; pin CLK grounded IOL = 200 A current limit IOL = 70 mA IOH = -200 A current limit IOH = -70 mA CL = 30 pF CL = 30 pF operational CL = 30 pF rise and fall; CL = 30 pF VCC = +5 V VCC = +3 V Control inputs: pins CLKDIV1 and RSTIN[6] VIL VIH Vhys IIL IIH LOW-level input voltage HIGH-level input voltage hysteresis voltage HIGH-level input current LOW-level input voltage HIGH-level input voltage hysteresis voltage HIGH-level input current control input VIH = VDD(INTF) LOW-level input current VIL = 0 V control input VIH = VDD(INTF) LOW-level input current VIL = 0 V -0.3 0.7 VDD(INTF) 0.3VDD(INTF) VDD(INTF) + 0.3 V V V A A 0.2 0.12 V/ns V/ns
[5] [5] [5]
Min 0 0 VCC - 0.4 0.9VCC 0 -
Typ -
Max 0.3 0.2 VCC VCC 0.4 0.1 0.1
Unit V V V V V s s
Clock output to the card: pin CLK 0 0 0 VCC - 0.4 0.9VCC 0 0 45 0.1 0.3 -1 0.3 VCC VCC 0.4 16 16 20 55 V V mA V V V V ns ns MHz %
0.14 VDD(INTF) 1 1
Control input: pin CMDVCCN[6] VIL VIH Vhys IIL IIH -0.3 0.7VDD(INTF) 0.14VDD(INTF) 0.3VDD(INTF) VDD(INTF) + 0.3 1 1 V V V A A
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Table 7. Characteristics of IC supply voltage ...continued VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min 5 V card; Figure 10 3 V card; Figure 11, Figure 12 Card detection input[6][7] VIL VIH Vhys IIL IIH LOW-level input voltage HIGH-level input voltage hysteresis voltage HIGH-level input current LOW-level output voltage HIGH-level output voltage pull-up resistance pin PRESN 0 V < VIH < VDD(INTF) LOW-level input current 0 V < VIL < VDD(INTF) -0.3 0.7VDD(INTF) 0.14VDD(INTF) 0.3VDD(INTF) VDD(INTF) + 0.3 5 5 V V V A A 30 Typ Max 100 15 Unit Hz ms ms fCMDVCCN frequency on pin CMDVCCN tw pulse width
OFFN output[8] VOL VOH Rpu
[1] [2] [3] [4] [5] [6] [7] [8]
IOL = 2 mA IOH = -15 A connected to VDD(INTF)
0
-
0.3 24
V V k
0.75VDD(INTF) 16 20
To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 220 nF and one 470 nF. Using decoupling capacitors of one 220 nF 20 % and one 470 nF 20 %. Using the integrated 9 k pull-up resistor connected to VCC. Using the integrated 10 k pull-up resistor connected to VDD(INTF). The transition time and the duty factor definitions are shown in Figure 13 on page 19; = t1 / (t1 + t2). Pins PRESN and CMDVCCN are active LOW; pin RSTIN is active HIGH; see Table 4 for states of pin CLKDIV1. Pin PRESN has an integrated current source of 1.25 A to VDD(INTF). Pin OFFN is an NMOS drain, using an internal 20 k pull-up resistor connected to VDD(INTF).
Table 8. Symbol IOlim
Protection characteristics Parameter output current limit Conditions pin I/O pin VCC pin CLK pin RST Min -15 135 -70 -20 90 Typ 175 120 150 Max +15 225 +70 +20 150 Unit mA mA mA mA mA C
Isd Tsd
shutdown current shutdown temperature
pin VCC at die
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Table 9. Symbol tact tdeact td
Timing characteristics Parameter activation time deactivation time delay time Conditions see Figure 9 on page 12 see Figure 7 on page 10 CLK sent to card using an external clock td(start) = t3; see Figure 6 on page 9 td(end) = t5; see Figure 6 on page 9 2090 2120 3.2 4.5 4112 4160 6.4 s s ms Min 2090 35 Typ 90 Max 4160 250 Unit s s
tdeb
debounce time
pin PRESN
tr 90 % 90 %
tf VOH (VOH + VOL) / 2
10 %
t1
10 %
t2
VOL
001aai973
Fig 13. Definition of output and input transition times
12. Application information
VDD(INTF)
MICROCONTROLLER
VDD(INTF)
C1 100 nF
XTAL1 XTAL2 VDD(INTF) RSTIN CMDVCCN CLKDIV1 PRESN I/O
TDA8034T TDA8034AT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
I/OUC OFFN VDD VDDP VCC RST CLK GND VDD
C2 100 nF C3 100 nF C4 10 F
VDDP
CARD CONNECTOR C5 C6 C7 C8 C1 C2 C3 C4
C6 220 nF C5 470 nF
R4 0
001aal003
Fig 14. Application diagram
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13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D
E
A X
c y HE vMA
Z
16 9
Q A2 pin 1 index Lp
1 8
A1
(A 3)
A
L wM detail X
e
bp
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
o
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 15. Package outline SOT109-1 (SO16)
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14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 11. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 16.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 12. Acronym EMV ESD ESR FCDM HBM LDO MM NMOS POR Abbreviations Description Europay MasterCard VISA ElectroStatic Discharge Equivalent Series Resistor Field Charged Device Model Human Body Model Low Drop-Out Machine Model Negative-channel Metal-Oxide Semiconductor Power-On Reset
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16. Revision history
Table 13. Revision history Release date 20101112 Data sheet status Product data sheet Change notice Supersedes TDA8034T_TDA8034AT_1 Document ID TDA8034T_TDA8034AT v.2.0 Modifications:
*
Table 3 "Pin description": Table note [5] VDD changed into VDD(INTF) Table note [6] added IOUC, AUX1UC, AUX2UC referenced to new note [6] Product data sheet -
TDA8034T_TDA8034AT_1
20100205
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
17.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
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product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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19. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Clock configuration . . . . . . . . . . . . . . . . . . . . . .7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13 Thermal characteristics . . . . . . . . . . . . . . . . . .13 Characteristics of IC supply voltage . . . . . . . .14 Protection characteristics . . . . . . . . . . . . . . . .18 Timing characteristics . . . . . . . . . . . . . . . . . . .19 SnPb eutectic process (from J-STD-020C) . . .22 Lead-free process (from J-STD-020C) . . . . . .22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .23 Revision history . . . . . . . . . . . . . . . . . . . . . . . .24
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20. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration (SO16) . . . . . . . . . . . . . . . . . . . .4 Voltage supervisor circuit . . . . . . . . . . . . . . . . . . . .5 Voltage supervisor waveforms . . . . . . . . . . . . . . . .6 Basic layout for using an external clock. . . . . . . . .7 Activation sequence at t3. . . . . . . . . . . . . . . . . . . .9 Deactivation sequence . . . . . . . . . . . . . . . . . . . .10 Emergency deactivation sequence after card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and VCC . . . . . . . . . . . . . . .12 Card activation, VCC = 5 V, t0 > 30 ms. . . . . . . . .12 Card activation, VCC = 3 V, t0 < 15 ms. . . . . . . . .12 Card activation, VCC = 3 V, t0 > 15 ms. . . . . . . . .13 Definition of output and input transition times . . .19 Application diagram . . . . . . . . . . . . . . . . . . . . . . .19 Package outline SOT109-1 (SO16) . . . . . . . . . . .20 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
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Smart card interface
21. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 5 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 5 Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Input and output circuits . . . . . . . . . . . . . . . . . . 7 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8 Activation sequence . . . . . . . . . . . . . . . . . . . . . 8 Deactivation sequence . . . . . . . . . . . . . . . . . . . 9 VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 10 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 10 Automatic determining of card supply voltage 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact information. . . . . . . . . . . . . . . . . . . . . 26 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 November 2010 Document identifier: TDA8034T_TDA8034AT

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